1. Field of the Invention
The present invention relates to a variable gain amplifier which is widely used for an analog integrated circuit in a communication system, and more particularly, to a low-power variable gain amplifier having a direct current (DC) bias stabilizer.
2. Description of the Related Art
A variable gain amplifier is used to maintain a strength of an output signal when a strength of an input signal is changed or change a strength of an output signal when a strength of an input signal is constant by changing a gain value.
FIG. 1 is a circuit diagram illustrating a conventional variable gain amplifier without a direct-current (DC) bias stabilization scheme.
Referring to FIG. 1, the variable gain amplifier 100 without the DC bias regulation scheme includes a variable gain amplifying unit 110, two load resistors 115 and 116, two differential input signal sources Iin+ and Iin−.
The first and second differential input signals Iin+ and Iin− are defined by Equations 1 and 2.Iin+=IDC+IAC  [Equation 1]Iin−=IDC−IAC  [Equation 2]
Referring to Equations 1 and 2, the first and second differential input current signals Iin+ and Iin− have the same DC current IDC and have alternating-currents (AC) IAC having a phase difference of 180°.
The AC currents IAC of the first and second differential input current signals Iin+ and Iin− pass through the variable gain amplifying 110 including first, second, third, and fourth transistors 111, 112, 113, and 114 and are changed into voltages by the first and second resistors 115 and 116 that are the toad resistors to form first and second differential output voltage signals Vout+ and Vout−.
The sum of currents flowing through the first and second transistors 111 and 112 is the same as a current of the first differential input current signal Iin+. Similarly, the sum of currents flowing through the third and fourth transistors 113 and 114 is the same as a current of the second differential input current signal Iin−.
Voltage levels of the first and second gain control signals Vcp and Vcn that control an output gain determine currents flowing through the first to fourth transistors 111 to 114. Here, the current of the first differential output current signal Iout+ passing through the first transistor 111 determines the voltage level of the first differential output voltage signal Vout+, and the current of the second differential output current signal Iout− passing through the fourth metal-oxide-semiconductor (MOS) transistor determines the voltage level of the second differential output voltage signal Vout−.
A gain k of the variable gain amplifier 110 is defined as a ratio of a current value of the first differential input current signal Iin+ to a current value of the first differential output current signal Iout+, or a ratio of a current value of the second differential input current signal Iin− to a current value of the second differential output current signal Iout−. Therefore, as the currents flowing through the first and fourth transistors 111 and 114 increase, the gain increases, and this means that the voltage level of the first gain control signal Vcp has to be higher than that of the second gain control signal Vcn.
The first and second differential output current signals Iout+ and Iout− are represented by Equations 3 and 4 as follows.Iout+=kIin+=k(IDC+IAC)  [Equation 3]Iout−=kIin−=k(IDC−IAC)  [Equation 4]
The conventional variable gain amplifier illustrated in FIG. 1 has a problem in that the DC currents flowing through the first and second resistors 115 and 116 are changed, as the gain is changed by controlling the voltage levels of the first and second gain control signals Vcp and Vcn. Therefore, a DC voltage dropped across the first and second resistors 115 and 116 is changed, and reference voltage levels of the two differential output voltage signals Vout+ and Vout− output from the variable gain amplifier are changed.
In order to solve the problem, two capacitors 117 and 118 are used to transmit only an AC signal. However, there is another problem in that the low-frequency differential output voltage signals Vout+ and Vout− are blocked by the capacitors so as not to be transmitted to a next function block.
In order to solve the problem, a variable gain amplifier using a DC bias stabilization scheme is proposed.
FIG. 2 is a circuit diagram illustrating a conventional variable gain amplifier having a DC bias stabilization scheme.
Referring to FIG. 2, the variable gain amplifier 200 having the DC bias stabilization scheme includes a second variable gain amplifying unit 220 having the same structure as that of a first variable gain amplifying unit 210. The second variable gain amplifier 220 is connected with two auxiliary current sources 250 and 260. A DC current that has the same value as the first and second differential input current signals Iin+ and Iin− of the first variable gain amplifier 210 flows through the added two auxiliary current sources 250 and 260. However, an AC current does not flow therethrough.
The second variable gain amplifier 220 includes four transistors 221, 222, 223, and 224. Connection relationships between the four transistors 221, 222, 223, and 224 and the first and second gain control signals Vcp and Vcn are opposite to those of the first variable gain amplifier 210.
In a structure in which the two variable gain amplifiers 210 and 220 and the two gain control signals Vcp and Vcn are crossed and connected, when a voltage of the first gain control signal Vcp increases, a DC current and an AC current that flow through the first and second resistors 215 to the first transistor 211 increases. However, the DC current and the AC current that flow to the eighth transistor 224 decreases. Here, only the DC current flows through the second auxiliary current source 250, so that only the DC current flows through the eighth transistor 224, and the AC current of the first differential output current signal Iout+ is not affected.
On the other hand, as the voltage of the first gain control signal Vcp is decreased, the DC current and the AC current flowing from a first source voltage Vdd through the first and second resistors 215 and 216 to the first transistor 211 decreases. However, the DC current and the AC current flowing through the eight transistor 224 increase.
As described above, a constant DC current flows through the first and second resistors 215 and 216, irrespective of the voltage of the first gain control signal Vcp, so that constant DC voltages of output nodes Vout+ and Vout− are maintained.
However, the conventional variable gain amplifier 200 having the DC bias stabilization scheme illustrated in FIG. 2 requires two times the current of the conventional variable gain amplifier 100 illustrated in FIG. 1, so that relatively high power consumption is required. Therefore, the aforementioned scheme cannot be applied to a low-power apparatus.